library ieee;
use ieee.std_logic_1164.all;

entity tb_controlador is
end tb_controlador;

architecture a_tb_controlador of tb_controlador is

	component controlador
		port(
			cp, ep, ea, su, eu, clk_out, clr_out: out std_logic;
	   	ce_not, lm_not, li_not, ei_not, la_not, lb_not, l0_not, clk_not_out, clr_not_out: out std_logic;
	   	instruction: in std_logic_vector (3 downto 0)
		);
	end component;
	
   for controlador_0: controlador use entity work.controlador;
   
  	signal erro : boolean := false; -- para parar a simulação
  	
  	signal tb_cp, tb_ep, tb_ea, tb_su, tb_eu, tb_clk_out, tb_clr_out: std_logic;
	signal tb_ce_not, tb_lm_not, tb_li_not, tb_ei_not, tb_la_not, tb_lb_not, tb_l0_not, tb_clk_not_out, tb_clr_not_out: std_logic;
	signal tb_instruction: std_logic_vector (3 downto 0) := "0000";
  	
  	begin
  	controlador_0: controlador port map (tb_cp, tb_ep, tb_ea, tb_su, tb_eu, tb_clk_out, tb_clr_out,
  													 tb_ce_not, tb_lm_not, tb_li_not, tb_ei_not, tb_la_not, tb_lb_not, tb_l0_not, tb_clk_not_out, tb_clr_not_out,
  													 tb_instruction);

	tb_instruction <= "0001" after 560 ns,  -- instrucao ADD
							"0010" after 1040 ns, -- instrucao SUB
							"1110" after 1520 ns, -- instrucao OUT
							"1111" after 2000 ns; -- instrucao HLT
	
	process
	begin

		------------------------------ Instrucao LDA ------------------------------

    	wait for 100 ns;
		-- t1 do LDA
    	if(not (tb_ep='1' AND tb_lm_not='0')) then
	  		erro<=true;
		end if;
    	
    	wait for 80 ns; -- 180 ns
    	-- t2 do LDA
    	if(not (tb_cp='1')) then
    		erro<=true;
    	end if;
    	
    	wait for 80 ns; -- 260 ns
    	-- t3 do LDA
    	if(not (tb_ce_not='0' AND tb_li_not='0')) then
    		erro<=true;
    	end if;
    	
    	wait for 80 ns; -- 340 ns
    	-- t4 do LDA
    	if(not (tb_ei_not='0'AND tb_lm_not='0')) then
    		erro<=true;
    	end if;
    	
    	wait for 80 ns; -- 420 ns
    	-- t5 do LDA
    	if(not (tb_ce_not='0' AND tb_la_not='0')) then
    		erro<=true;
    	end if;
    	
    	wait for 80 ns; -- 500 ns
    	-- t6 do LDA
    	if(not (tb_ce_not='1' AND tb_la_not='1')) then
    		erro<=true;
    	end if;
    	
		------------------------------ Instrucao ADD ------------------------------
    	
		wait for 80 ns; -- 580 ns
		-- t1 do ADD
    	if(not (tb_ep='1' AND tb_lm_not='0')) then
	  		erro<=true;
		end if;

    	wait for 80 ns; -- 660 ns
    	-- t2 do ADD
    	if(not (tb_cp='1')) then
    		erro<=true;
    	end if;
    	
    	wait for 80 ns; -- 740 ns
    	-- t3 do ADD
    	if(not (tb_ce_not='0' AND tb_li_not='0')) then
    		erro<=true;
    	end if;
    	
    	wait for 80 ns; -- 820 ns
    	-- t4 do ADD
    	if(not (tb_ei_not='0' AND tb_lm_not='0')) then
    		erro<=true;
    	end if;

    	wait for 80 ns; -- 900 ns
    	-- t5 do ADD
    	if(not (tb_ce_not='0' AND tb_lb_not='0')) then
    		erro<=true;
    	end if;

    	wait for 80 ns; -- 980 ns
    	-- t6 do ADD
    	if(not (tb_eu='1' AND tb_la_not='0')) then
    		erro<=true;
    	end if;
    	
		------------------------------ Instrucao SUB ------------------------------

		wait for 80 ns; -- 1060 ns
		-- t1 do SUB
    	if(not (tb_ep='1' AND tb_lm_not='0')) then 
	  		erro<=true;
		end if;

    	wait for 80 ns; -- 1140 ns
    	-- t2 do SUB
    	if(not (tb_cp='1')) then
    		erro<=true;
    	end if;
    	
    	wait for 80 ns; -- 1220 ns
    	-- t3 do SUB
    	if(not (tb_ce_not='0' AND tb_li_not='0')) then
    		erro<=true;
    	end if;
    	
    	wait for 80 ns; -- 1300 ns
    	-- t4 do SUB
    	if(not (tb_ei_not='0' AND tb_lm_not='0')) then
    		erro<=true;
    	end if;

    	wait for 80 ns; -- 1380 ns
    	-- t5 do SUB
    	if(not (tb_ce_not='0' AND tb_lb_not='0')) then
    		erro<=true;
    	end if;

    	wait for 80 ns; -- 1460 ns
    	-- t6 do SUB
    	if(not (tb_eu='1' AND tb_la_not='0' AND tb_su='1')) then
    		erro<=true;
    	end if;

		------------------------------ Instrucao OUT ------------------------------
		
		wait for 80 ns; -- 1540 ns
		-- t1 do OUT
    	if(not (tb_ep='1' AND tb_lm_not='0')) then
	  		erro<=true;
		end if;

    	wait for 80 ns; -- 1620 ns
    	-- t2 do OUT
    	if(not (tb_cp='1')) then
    		erro<=true;
    	end if;
    	
    	wait for 80 ns; -- 1700 ns
    	-- t3 do OUT
    	if(not (tb_ce_not='0' AND tb_li_not='0')) then
    		erro<=true;
    	end if;
    	
    	wait for 80 ns; -- 1780 ns
    	-- t4 do OUT
    	if(not (tb_ea='1' AND tb_l0_not='0')) then
    		erro<=true;
    	end if;
    	
    	assert false report "### Simulação encerrada com sucesso!" severity failure;

   end process;

	assert not erro report "### ERRO!" severity failure;
	
end a_tb_controlador;
